library verilog;
use verilog.vl_types.all;
entity lab2_fre_div2_021_vlg_sample_tst is
    port(
        C_068           : in     vl_logic;
        S0_068          : in     vl_logic;
        sampler_tx      : out    vl_logic
    );
end lab2_fre_div2_021_vlg_sample_tst;
